Staff ML Engineer

• Job Title: Staff ML Engineer (Full-Stack: Model to Silicon)
• Location: San Jose, CA (On-site)
• Work Arrangement: On-site
• Job Type: Contract

Industry: Semiconductor / Hardware Security / AI Acceleration

About the Role:

We are seeking a Staff ML Engineer to own the end-to-end path from model design down to silicon execution. In this role, you will bridge algorithmic deep learning and low-level NPU/accelerator constraints, engineering inference and training pipelines where latency budgets, SRAM/memory bandwidth, and power constraints are primary drivers.

Key Responsibilities:

• Design, train, evaluate, and productize deep learning architectures optimized directly for hardware targets.
• Optimize distributed training and inference runtimes across GPU clusters and custom AI-accelerator/NPU silicon.
• Extend and harden NPU architectures (e.g., RISC-V RVV, custom tensor cores) for production silicon integration.
• Build low-overhead inference engines and serving runtimes in C/C++ conforming to strict power and memory footprints.
• Interface below the application layer as needed, including embedded Linux, RTOS (e.g., Zephyr), and BMC firmware.
• Develop automated verification and test harnesses for silicon bring-up, post-silicon validation, or AI-assisted RTL/DV.

Qualifications:

• Master’s degree required; PhD preferred (Computer Science, Computer Engineering, Electrical Engineering, or related discipline).
• 5–7+ years of hands-on production experience training and deploying machine learning models.
• Demonstrated mastery of hardware-aware ML (quantization, graph compilers, low-level runtime optimization, memory tiling).
• Proven depth in at least 2 of the following 5 focus areas:
• NPU / AI-Accelerator: RVV, MAC/tensor engine mapping, or RTL/DV integration.
• Low-Level Systems: Embedded Linux, RTOS (Zephyr/FreeRTOS), or BMC/firmware development.
• Inference Runtimes: Custom C/C++ inference engine design under strict memory constraints.
• Hardware Validation: Automated bring-up harnesses, post-silicon validation, or manufacturing test loops.
• Hardware Security / AI Sec: Telemetry analysis, intrusion detection, or firmware-level security ML.